![]() ![]() E.g., Intel’s PREFETCHW instruction requests that the cache line be loaded in anticipation of a store to the line. ![]() The instruction definition is written in terms of specific transactions on a model architecture (with caveats that an implementation might do something different).A cache transaction is requested, but it is not required for correctness.The Intel CLWB instruction was added for this purpose - see E.g., In a system with some non-volatile memory, a processor must have a way to guarantee that dirty data has been written from the (volatile) caches to the non-volatile memory.The specified cache transaction must take place to guarantee correctness.Instructions that directly pertain to caching can be grouped into three categories: If you are not a “cache hint instruction” enthusiast, this may not seem like a big deal, but it actually represents a relatively important shift in instruction design philosophy. Intel’s instruction description mentions this use case explicitly.Cache-to-Cache Intervention Optimization: The cache line is expected to be accessed soon by a different core, and cache-to-cache interventions may be faster if the data is not in the closest level(s) of cache. ![]()
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